Embedded analog circuits such as phase lock loops (PLLs), voltage controlled oscillators (VCOs), digital to analog converters (DACs), analog to digital converters (ADCs), and radio frequency (RF) transceivers rely on a wide bandwidth noise-free power supply voltages to meet phase-noise, timing-jitter, spurious-free dynamic range, and low-noise figure requirements in individual blocks.
FIG. 1 is an example integrated circuit die block diagram of a SoC 100 utilizing multiple LDOs 110 connected to multiple circuit blocks 120 tied to a common externally supplied voltage VDD.
As more SoC designs progress toward embedding more analog circuits along with digital processors in the same silicon die, it is desirable to include independent low-noise voltage regulators for each embedded analog core to improve circuit isolation.
Low Drop-Out (LDO) voltage regulators have been traditionally used to meet this requirement. However, it is a design challenge to implement a wide bandwidth power supply rejection ratio (PSRR) LDO voltage regulator using only on-chip components.
Traditionally phase lock loops (PLLs) and embedded analog cores use independent power-supply bumps to get a clean power supply connection. The number of power-supply bumps and silicon die bond pads increases as multiple PLLs and embedded analog cores are integrated into a system-on-chip (SoC).
The power-supply bumps refer to a solder ball connection between a packaged integrated circuit (IC) and the main application circuit board. By incorporating LDO voltage regulators on the IC, the number of power-supply and ground connections can be minimized, thereby reducing the packaged IC pin count, chip and main application circuit board routing complexity.
FIG. 2 is a schematic diagram of a known single-stage low drop-out (LDO) voltage regulator. A typical single stage LDO voltage regulator 200, as shown, may be implemented using an error amplifier circuit 202 driving a common-source P-channel metal oxide semiconductor (PMOS) device 204. PMOS device 204 has a decoupling capacitor (CL) 205 coupled at the drain D of PMOS device 204 to suppress power-supply noise leakage from an input voltage VDD. At the drain D of PMOS device 204 is an output node VREG. PMOS device 204 is usually large (in terms of integrated circuit die area) to maintain the voltage drop low across PMOS device 204 (VDD-VREG). Node VREG is also connected to an integrated circuit (IC) load 208. IC load 208 includes the decoupling capacitor (CL) 205 which is in parallel with a resistive load (RL) 209 and a current device (IL) 210.
The configuration of PMOS device 204 and IC load 208 results in two closely-spaced poles that require compensation for stability. In general, a Miller-compensation capacitor (Cc) 206 is used to realize a dominant pole at gate G of PMOS device 204. However, the Miller-compensation capacitor (Cc) 206 results in a zero in the transfer function between the supply voltage (VDD) to LDO voltage regulator output voltage (VREG) (herein after referred to the “supply-to-output transfer function”). A zero in the supply-to-output transfer function compromises the power supply rejection ratio (PSRR) at frequencies above the stated zero frequency.
A reference voltage VREF is provided on the inverting terminal 211 of the error amplifier circuit 202. The output voltage from the error amplifier circuit 202 is denoted as Vout. A feedback loop extends from the VREG node to the non-inverting terminal 212 of the error amplifier circuit 202. VREF is typically provided by a precision band-gap reference and is equal to the desired VREG voltage. Alternatively, VREF may be a programmable voltage by using a band-gap reference in conjunction with a digital-to-analog converter to set the desired VREG voltage.
FIG. 3 is an example graph of the wide bandwidth supply rejection from VDD (input) to VREG (output) vs. Frequency (Hz) for the single-stage LDO voltage regulator shown in FIG. 2.
As shown in FIG. 3, the supply rejection from VDD to VREG vs. Frequency (Hz), for LDO voltage regulator 200 of FIG. 2, may be compromised by the zero frequency location. The rejection is limited to −40 dB at low frequencies (less than 400 kHz in this example) and worsens from approximately 1 MHz to 10 GHz as a result of the zero in the transfer function. The worst case supply rejection is approximately −15 dB at 100 MHz in this example. In the presence of wide bandwidth noise on the VDD source voltage, an LDO voltage regulator, with such poor PSRR, will compromise analog circuit block performance in PLLs, VCOs, DACs, ADCs, and RF transceivers utilizing a suitable VREG output voltage.
There is a need therefore for a low drop-out (LDO) voltage regulator integrated circuit with improved wide bandwidth power supply rejection ratio (PSRR).